1. Field
Exemplary embodiments of the present invention relate to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device having a well-pickup contact structure and a method for fabricating the semiconductor device.
2. Description of the Related Art
Semiconductor device, such as non-volatile memory devices, includes patterns for applying a bias voltage to operate memory cells. For example, a NAND flash memory device includes memory cells that are coupled serially, selection transistors that are coupled on both sides of the memory cells, and a structure for applying a predetermined bias to wells formed in active regions of a semiconductor substrate where the memory cells and the selection transistors are disposed.
FIGS. 1A and 1B illustrate a conventional semiconductor device, and a method for fabricating the semiconductor device.
Referring to FIGS. 1A and 1B, an isolation layer 20 is formed over a substrate 10 to define a plurality of active regions 10A that are stretched in parallel to each other, and then a first insulation layer 30 is formed over the active regions 10A and the isolation layer 20.
Subsequently, first drain contact plugs 40A are formed to be coupled with drain regions through the first insulation layer 30, and a first well-pickup contact plug 40B is formed to be coupled with well-pickup regions. Also, a well-pickup contact pad 40C is formed to be coupled with the first well-pickup contact plug 40B, and a second insulation layer 50 is formed over the resultant substrate including the first drain contact plugs 40A, the first well-pickup contact plug 40B, and the well-pickup contact pad 40C.
Subsequently, second drain contact plugs 60A coupled with the first drain contact plugs 40A through the second insulation layer 50 and a second well-pickup contact plug 60B coupled with the well-pickup contact pad 40C are formed, and then a third insulation layer 70 is formed over the resultant substrate including the second drain contact plugs 60A and the second well-pickup contact plug 60B. Subsequently, a conductive pad 80A that is coupled with the second well-pickup contact plug 60B through the third insulation layer 70, dummy lines 80B on both sides of the conductive pad 80A, and conductive lines 80C coupled with the second drain contact plugs 60A are formed.
Since the first well-pickup contact plug 40B is formed between the first drain contact plugs 40A according to conventional technology, misalignments may be caused between a series of the first drain contact plugs 40A. In particular, as the first well-pickup contact plug 40B may be enlarged in size, substrate loss and chip size may be increased.